This invention relates generally to semiconductor devices and more particularly the invention relates to an integrated transistor logic device utilizing conductance modulation to increase transconductance and switching speed.
The conductance modulated transistor pair is described in my U.S. Pat. No. 4,920,399 and copending U.S. patent application Ser. No. 07/528,950, supra. These devices have increased conductance and operating speed by merging complementary bipolar transistors in complementary MOS transistors (CBiCMOS).
The use of Schottky injection of majority and minority carriers to increase the transconductance of an MOS transistor is discussed by Hall in U.S. Pat. No. 4,920,399 and minority carrier injection into an MOS transistor invention is described in U.S. patent application Ser. No. 07/528,950. These described inventions increase the circuit speed by increasing the transconductance of the MOS transistor while reducing the capacitance reflected to the drain/base node from the output load capacitance. This technique continues to increase the circuit speed until the FT (Unity gain operating frequency) of the bipolar transistor becomes a limiting term or the load capacitance becomes large and limiting in the case of the CBiCMOS structure. A speed of operation limitation of such devices is due to the large capacitance existing between the drain/base node of the transistors and ground. In the case of the Schottky structure the capacitance between the drain and ground is the speed limiting term under low capacitance load conditions.
The present invention is directed to modifying the CBiCMOS and the conductance modulated transistor structure to include a layer of dielectric isolation which surrounds a portion of the drain/base structure to reduce its capacitance and increase operating speed while reducing operating power. By using a layer of silicon oxide (SiO.sub.2) or silicon nitride (Si.sub.3 N.sub.4) dielectric beneath the inactive drain-emitter area a further increase in speed can be achieved over that of the previous inventions as a result of the reduced capacitance of the critical node. This structure is achieved by first forming a dielectric layer on the surface of the single crystal substrate, which is localized to the area underneath the drain contact. This step is done prior to the growth of the epitaxial layer in which the transistors are formed. The injecting edge of the emitter is formed in the single crystal portion of the epitaxial film just adjacent the polycrystalline silicon formed directly above the dielectric pad area.